Abstract: The dramatic growth in“smart”portable electronics is driving the need for a more sophisticated IC packaging approach that allows room for increasing functionality while meeting ever decreasing form factor requirements. Traditional solutions like Multi-Chip Modules （MCM） may not meet the intense I/O requirements and form factor restrictions concurrently. On the other hand, advanced solutions like 2.5D TSV silicon interposer may prove to be cost prohibitive, especially for applications serving cost-sensitive consumer markets. In the middle, however, embedded die packaging may strike the ideal combination with an increased I/O density, reduced footprint, and multi-die capability within a single IC package.

  Embedded die packaging itself is diverse and can be configured in a variety of architectures. Passive device embedding is discussed, but the paper focuses primarily on active die embedding. Active die embedding has two general constructions: either as a 2D fan-out package or a 3D stacked package for higher levels of system integration. The 2D formats include platforms such as Fan Out Wafer Level packaging （FO-WLP） and embedded die in laminate. One of the primary differences in the 2

  D structures is the processing format, the former on wafer and the latter on laminate panel. The choice between processing formats can have a significant impact on both cost and yield. The other difference between 2D formats is the timing of the die placement in the process flow. The benefits and disadvantages of “Die First”, “Die Last” and “Die Mid” placement are discussed. The other active embedded die format is the 3D stacked package format with a modular System in Package （SiP）approach. 3D formats have similar distinctions as 2D formats, only with the added element of stacking one or more packages for a true SiP architecture. This paper also covers the evolution of embedded die, along with its projected growth, packaging formats and future roadmaps